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ASAHI KASEI
[AK5394A]
AK5394A
Super High Performance 192kHz 24-Bit ADC
GENERAL DESCRIPTION The AK5394A is a 24bit, 192kHz sampling 2ch A/D Converter for professional digital audio systems. The modulator in the AK5394A uses the new developed advanced multi bit architecture. This new architecture achieves the wide dynamic range and wide bandwidth, while keeping superior distortion characteristics. The AK5394A performs 123dB dynamic range, so the device is suitable for professional studio equipment such as digital mixer, digital VTR etc. The operating voltages support analog 5V and digital 3.3V, so it is easy to I/F with 3.3V logic IC. FEATURES 128x Oversampling New advanced multi bit Architecture ADC Sampling Rate: 1kHz 216kHz Full Differential Inputs S/(N+D): 110dB DR: 123dB S/N: 123dB High Performance Linear Phase Digital Anti-Alias filter * Passband: 0 21.768kHz(@fs=48kHz) * Ripple: 0.001dB * Stopband: 120dB Digital HPF & Offset Calibration for Offset Cancel Power Supply: 5V5%(Analog), 3 5.25V(Digital) Power Dissipation: 665mW Package: 28pin SOP AK5392/3 Semi-Pin Compatible
SMODE1 SMODE2 12 VREFL+ VREFL1 2 11 SCLK LRCK 14 13 FSYNC 16 15 SDATA
Voltage Reference
Serial Output Interface
VCOML 3 4 AINL+ 5 AINL6 ZCAL 25 AINR+ 24 AINR26 VCOMR 28 VREFR+ 27 VREFR23 VA
Delta-Sigma Modulator
Decimation Filter
HPF
19 HPFE 17
Delta-Sigma Modulator
Decimation Filter
MCLK DFS0 DFS1
HPF
18 20
Voltage Reference
22 AGND 21 BGND
Controller
9 CAL 10 RSTN
Calibration SRAM
7 VD 8 DGND
MS0137-E-03 -1-
2005/05
ASAHI KASEI
[AK5394A]
Ordering Guide
AK5394AVS AKD5394A -10 +70C 28pin SOP AK5394A Evaluation Board
Pin Layout
VREFL+ VREFLVCOML AINL+ AINLZCAL VD DGND CAL RSTN SMODE2 SMODE1 LRCK SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24
VREFR+ VREFRVCOMR AINR+ AINR-
Top View
23 22 21 20 19 18 17 16 15
VA
AGND BGND DFS1 HPFE DFS0 MCLK FSYNC SDATA
Compatibility with AK5392/3
AK5394A Pin 2 Pin 18 Pin 20 Pin 27 fs (max) MCLK at 48kHz MCLK at 96kHz MCLK at 192kHz DR S/N VREFL- DFS0 DFS1 VREFR- 216kHz 256fs 128fs 64fs 123dB 123dB AK5393 GNDL DFS TEST GNDR 108kHz 256fs 128fs N/A 117dB 117dB AK5392 GNDL CMODE TEST GNDR 54kHz 256fs or 384fs N/A N/A 116dB 116dB
MS0137-E-03 -2-
2005/05
ASAHI KASEI
[AK5394A]
Common PCB layout example between AK5393 and AK5394A
AK5393
(Analog Ground) + 10u (short ) 0.1u 1 2 3 0.22u 4 5 +3.3~5V Digital + 6 7 8 10u 0.1u 9 10 11 12 13 14 VREFL+ GNDL VCOML AINL+ AINLZCAL VD DGND CAL RSTN SMODE2 SMODE1 LRCK SCLK VREFR+ GNDR VCOMR AINR+ AINRVA AGND BGND TEST HPFE DFS MCLK FSYNC SDATA 28 27 26 25 24 + 23 22 21 20 19 18 17 16 15 0.1u 10u 10u 0.1u 0.22u +5V Analog 0.22u 0.1u + 10u (short ) 10u + 10u 2 3 4 5 +3.3~5V Digital + 6 7 8 9 10 11 12 13 14 VREFLVCOML AINL+ AINLZCAL VD DGND CAL RSTN SMODE2 SMODE1 LRCK SCLK VREFRVCOMR AINR+ AINRVA AGND BGND DFS1 HPFE DFS0 MCLK FSYNC SDATA 27 26 25 24 + 23 22 21 20 19 18 17 16 15 0.1u 10u 0.22u +5V Analog + 0.22u 1 VREFL+ VREFR+ 28 + 10u
AK5394A
(Analog Ground) 0.22u + 10u
Pin# 2 18 20 27
AK5393 GNDL Connected to AGND DFS TEST GNDR Connected to AGND
AK5394A VREFL- Connected to AGND with a 10uF electrolytic capacitor, and connected to VREFL+ with a 0.22uF ceramic capacitor. DFS0 DFS1 VREFR- Connected to AGND with a 10uF electrolytic capacitor, and connected to VREFR+ with a 0.22uF ceramic capacitor.
MS0137-E-03 -3-
2005/05
ASAHI KASEI
[AK5394A]
PIN/FUNCTION
No. 1 Pin Name VREFL+ I/O O Function Lch Positive Reference Voltage, 3.75V Normally connected to AGND with a large electrolytic capacitor and connected to VREFL- with a 0.22F ceramic capacitor. Lch Negative Reference Voltage, 1.25V Normally connected to AGND with a large electrolytic capacitor and connected to VREFL+ with a 0.22F ceramic capacitor. Lch Common Voltage Pin, 2.75V Lch Analog positive input Pin Lch Analog negative input Pin Zero Calibration Control Pin This pin controls the calibration reference signal. "L" :VCOML and VCOMR "H" : Analog Input Pins (AINL, AINR) Digital Power Supply Pin, 3.3V Digital Ground Pin, 0V Calibration Active Signal Pin "H" means the offset calibration cycle is in progress. Offset calibration starts when RSTN pin goes "H". CAL goes "L" after 8704 LRCK cycles for DFS pin = "L", 17408 LRCK cycles for DFS pin = "H". Reset Pin When "L", the digital section is powered-down. Upon returning "H", an offset calibration cycle is started. An offset calibration cycle should always be initiated after power-up. Serial Interface Mode Select Pin MSB first, 2's compliment. SMODE2 SMODE1 MODE LRCK L L Slave mode : MSB justified : H/L L H Master mode : Similar to I2S : H/L H L Slave mode : I2S : L/H 2 : L/H H H Master mode : I S Left/Right Channel Select Clock Pin When RSTN pin = "L" in master mode, LRCK outputs "L".
2 3 4 5
VREFL- VCOML AINL+ AINL-
O O I I
6
ZCAL
I
7 8 9
VD DGND CAL
O
10
RSTN
I
11 12
SMODE2 SMODE1
I I
13
LRCK
I/O
MS0137-E-03 -4-
2005/05
ASAHI KASEI
[AK5394A]
Serial Data Clock Pin SDATA is clocked out on the falling edge of SCLK. Slave mode: SCLK requires more than 48fs clock. Master mode: AK5394A outputs following clocks as SCLK. 14 SCLK I/O Normal Speed Mode: 128fs Double Speed Mode: 64fs Quad Speed Mode: 64fs When RSTN pin = "L", SCLK outputs "L"(normal/double speed mode) or outputs the inverted MCLK (quad speed mode). Serial Data Output Pin 15 SDATA O MSB first, 2's complement. Frame Synchronization Signal Pin Slave mode: When "H", the data bits are clocked out on SDATA. In I2S mode, FSYNC is don't care. 16 FSYNC I/O Master mode: FSYNC outputs 2fs clock. FSYNC stays "L" during reset. Master Clock Input Pin DFS1 DFS0 MCLK fs(typ) L L 256fs 48kHz 17 MCLK I L H 128fs 96kHz H L 64fs 192kHz H H (N/A) (N/A) Sampling Speed Select Pin 0 DFS1 DFS0 fs(typ) L L 48kHz 18 DFS0 I L H 96kHz H L 192kHz H H (N/A) High Pass Filter Enable Pin 19 HPFE I "L": Disable "H": Enable Sampling Speed Select Pin 1 20 DFS1 I (see #18 DFS0) 21 BGND Substrate Ground Pin, 0V 22 AGND Analog Ground Pin, 0V 23 VA Analog Supply Pin, 5V 24 AINR- I Rch Analog negative input Pin 25 AINR+ I Rch Analog positive input Pin 26 VCOMR O Rch Common Voltage Pin, 2.75V Rch Negative Reference Voltage, 1.25V 27 VREFR- O Normally connected to AGND with a large electrolytic capacitor and connected to VREFR+ with a 0.22F ceramic capacitor. Rch Positive Reference Voltage, 3.75V 28 VREFR+ O Normally connected to AGND with a large electrolytic capacitor and connected to VREFR- with a 0.22F ceramic capacitor. Note: All digital inputs should not be left floating. MS0137-E-03 -52005/05
ASAHI KASEI
[AK5394A]
ABSOLUTE MAXIMUM RATINGS
(AGND, BGND, DGND = 0V; Note 1) Parameter Power Supplies: Analog Digital |BGND-DGND| (Note 2) Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Temperature (power applied) Storage Temperature Symbol VA VD GND IIN VINA VIND Ta Tstg min -0.3 -0.3 -0.3 -0.3 -10 -65 max 6.0 6.0 0.3 10 VA+0.3 VD+0.3 70 150 Units V V V mA V V C C
Notes: 1. All voltages with respect to ground. 2. AGND, BGND and DGND must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND, BGND, DGND = 0V; Note 1)
Parameter Power Supplies: (Note 3) Analog Digital Symbol VA VD min 4.75 3.0 typ 5.0 3.3 max 5.25 5.25 Units V V
Notes: 1. All voltages with respect to ground. 3. The power up sequence between VA and VD is not critical. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
MS0137-E-03 -6-
2005/05
ASAHI KASEI
[AK5394A]
ANALOG CHARACTERISTICS (Ta = 25C; VA=5.0V; VD=3.3V; AGND=BGND=DGND=0V; fs=48kHz; Signal Frequency=1kHz; 24bit Output; Measurement frequency=10Hz 20kHz; DFS0="L", DFS1="L"; External circuit: Figure 10 Inputted through XLR; unless otherwise specified)
Parameter Resolution Analog Input Characteristics: -1dBFS (Note4) -1dBFS fs=48kHz -20dBFS -60dBFS -1dBFS (Note4) fs=96kHz -1dBFS BW=40kHz -20dBFS -60dBFS -1dBFS fs=192kHz -20dBFS BW=80kHz -60dBFS Dynamic Range (-60dBFS with A-weighted) (Note4) S/N ( A-weighted) (Note4) Interchannel Isolation Interchannel Gain Mismatch Gain Drift After calibration, HPF=OFF Offset Error After calibration, HPF=ON Offset Drift (HPF=OFF) Offset Calibration Range (HPF=OFF) (Note5) Input Voltage (AIN+) - (AIN-) S/(N+D) Power Supplies: Power Supply Current VA VD (fs=48kHz; DFS0="L", DFS1="L") (fs=96kHz; DFS0="H", DFS1="L") (fs=192kHz; DFS0="L", DFS1="H") Power Dissipation Power Supply Rejection (Note 6) 127 9 13 21 665 70 165 13.5 20 32 870 mA mA mA mA mW dB 87 87 117 117 110 110 94 100 60 110 94 97 57 94 92 52 123 120 123 120 120 0.1 150 1000 1 10 50 2.4 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB ppm/C LSB24 LSB24 LSB24/C mV V min Typ Max 24 Units Bits
0.5 2.55
2.25
Notes: 4. Using the circuit as shown in Figure9 (Analog input buffer circuit example 1). 1000F capacitors connected between VREF+/- pin and GND. 5. The output level reduces equivalent to DC offset after calibration. 6. PSRR is applied to VA and VD with 1kHz, 20mVpp.
MS0137-E-03 -7-
2005/05
ASAHI KASEI
[AK5394A]
FILTER CHARACTERISTICS (fs=48kHz) (Ta=25C; VA=5.0V5%; VD=3.0 5.25V; fs=48kHz, DFS0="L", DFS1="L") Parameter Symbol min typ ADC Digital Filter(Decimation LPF): Passband (Note 7) PB 0 Stopband (Note 7) SB 26.232 Passband Ripple PR Stopband Attenuation (Note 8) SA 120 Group Delay Distortion 0 GD Group Delay (Note 9) GD 63 ADC Digital Filter(HPF): Frequency response (Note 7) -3dB FR 1.0 6.5 -0.1dB FILTER CHARACTERISTICS (fs=96kHz) (Ta=25C; VA=5.0V5%; VD=3.0 5.25V; fs=96kHz, DFS0="H", DFS1="L") Parameter Symbol min typ ADC Digital Filter(Decimation LPF): Passband (Note 7) PB 0 Stopband (Note 7) SB 52.464 Passband Ripple PR Stopband Attenuation (Note 10) SA 120 Group Delay Distortion 0 GD Group Delay (Note 9) GD 63 ADC Digital Filter(HPF): Frequency response (Note 7) -3dB FR 1.0 6.5 -0.1dB FILTER CHARACTERISTICS (fs=192kHz) (Ta=25C; VA=5.0V5%; VD=3.0 5.25V; fs=192kHz, DFS0="L", DFS1="H") Parameter Symbol min typ ADC Digital Filter(Decimation LPF): Passband (Note 7) PB 0 Stopband (Note 8) SB 104.928 Passband Ripple PR Stopband Attenuation (Note 11) SA 120 Group Delay Distortion 0 GD Group Delay (Note 9) GD 63 ADC Digital Filter(HPF):
Frequency response (Note 7) -3dB -0.1dB FR 1.0 6.5
max 21.768 0.001
Units kHz kHz dB dB s 1/fs Hz Hz
max 43.536 0.003
Units kHz kHz dB dB s 1/fs Hz Hz
max 87.072 0.007
Units kHz kHz dB dB s 1/fs Hz Hz
MS0137-E-03 -8-
2005/05
ASAHI KASEI
[AK5394A]
Notes: 7. The passband and stopband frequencies are proportional to fs. 8. The analog modulator samples the input at 6.144MHz for an output word rate of 48kHz. There is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 6.144MHz 21.768kHz, where n=1,2,3***). 9. The calculating delay time which takes place due to the digital filtering process. This time is taken from when the analog signal ia input, to the time of setting the 24-bit data (from both channels) to the output register. 65/fs typ. (normal/double/quad speed mode) at HPF=ON. 10. The analog modulator samples the input at 6.144MHz for an output word rate of 96kHz. There is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 6.144MHz 43.536kHz, where n=1,2,3***) 11. The analog modulator samples the input at 6.144MHz for an output word rate of 192kHz. There is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 6.144MHz 87.072kHz, where n=1,2,3***).
DIGITAL CHARACTERISTICS (Ta=25C; VA=5.0V5%; VD = 3.0 5.25V) Parameter Symbol min High-Level Input Voltage VIH 70%VD Low-Level Input Voltage VIL High-Level Output Voltage Iout=-100A VOH VD-0.5 VOL Low-Level Output Voltage Iout= 100A Input Leakage Current Iin -
typ -
max 30%VD 0.5 10
Units V V V V A
MS0137-E-03 -9-
2005/05
ASAHI KASEI
[AK5394A]
SWITCHING CHARACTERISTICS (Ta=25C; VA=5.0V5%; VD=3.0 5.25V; CL=20pF) Parameter Symbol min Control Clock Frequency 0.256 fCLK Master Clock 29 tCLKL Pulse width Low 29 tCLKH Pulse width High fSLK Serial Data Output Clock (SCLK) 1 fs Channel Select Clock (LRCK) 25 duty cycle Serial Interface Timing (Note 12) Slave Mode (SMODE1 = "L") SCLK Period (Note 13) 1/128fs tSLK Normal Speed Mode 1/64fs tSLK Double Speed Mode 1/64fs tSLK Quad Speed Mode 33 tSLKL SCLK Pulse width Low 33 tSLKH Pulse width High 20 tSLR SCLK rising to LRCK Edge (Note 14) 20 tLRS LRCK Edge to SCLK rising (Note 14) tDLR LRCK Edge to SDATA MSB Valid tDSS SCLK falling to SDATA Valid tSF SCLK falling to FSYNC Edge -20 Master Mode (SMODE1 = "H") SCLK Frequency fSLK Normal Speed Mode fSLK Double Speed Mode fSLK Quad Speed Mode dSLK SCLK duty cycle fFSYNC FSYNC Frequency dFSYNC FSYNC duty cycle -20 tMSLR SCLK falling to LRCK Edge tLRF LRCK Edge to FSYNC rising tDSS SCLK falling to SDATA Valid tSF SCLK falling to FSYNC Edge -20 Reset / Calibration timing 150 tRTW RSTN Pulse width tRCR RSTN falling to CAL rising RSTN rising to CAL falling (Note 15) tRCF Normal Speed Mode tRCF Double Speed Mode tRCF Quad Speed Mode RSTN rising to SDATA Valid (Note 15) tRTV Normal Speed Mode tRTV Double Speed Mode tRTV Quad Speed Mode
typ 12.288
max 13.824
Units MHz ns ns MHz kHz %
6.144 48
13.824 216 75
20 20 20
ns ns ns ns ns ns ns ns ns ns
128fs 64fs 64fs 50 2fs 50 20 1 20 20
Hz Hz Hz % Hz % ns tSLK ns ns ns ns 1/fs 1/fs 1/fs 1/fs 1/fs 1/fs
50 8704 17408 34816 8719 17423 34831
Notes: 12. Refer to Serial Data Interface Section. 13. At Slave Mode, SCLK must be continuously provided more than 16fs at LRCK="H" and "L". 14. Specified LRCK edges not to coincide with the rising edges of SCLK. 15. The number of the LRCK rising edges after RSTN pin brought high.
MS0137-E-03 - 10 -
2005/05
ASAHI KASEI
[AK5394A]
Timing Diagram
LRCK tSLR tLRS
tSLK tSLKL
tSLKH
SCLK tDLR SDATA MSB MSB-1 tDSS MSB-2
Serial Data Timing (Slave Mode, FSYNC = "H")
LRCK tLRS tSLR SCLK tSF FSYNC tSF
tDLR SDATA MSB
tDSS D1 D0
Serial Data Timing (Slave Mode)
LRCK tSLR tLRS
tSLK tSLKL
tSLKH
SCLK tDSS SDATA MSB tDSS MSB-1
Serial Data Timing (I2S Slave Mode, FSYNC = Don't Care)
MS0137-E-03 - 11 -
2005/05
ASAHI KASEI
[AK5394A]
LRCK tMSLR SCLK tSF FSYNC tLRF tSF
tDSS SDATA MSB MSB-1
Serial Data Timing (Master Mode & I2S Master Mode, Normal Speed Mode)
tRTW RSTN
tRTV
tRCF
CAL tRCR
SDATA
Reset & Calibration Timing
MS0137-E-03 - 12 -
2005/05
ASAHI KASEI
[AK5394A]
OPERATION OVERVIEW System Clock Input
The external clocks that are required to operate the AK5394A are MCLK, LRCK(fs) and SCLK. MCLK should be synchronized with LRCK but the phase is free of care. Table 1 and 2 show the relationship between the sampling rate and the frequencies of MCLK and SCLK. As the AK5394A includes the phase detect circuit for LRCK, the AK5394A is reset automatically when the synchronization is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up. All external clocks must be present unless RSTN pin = "L", otherwise excessive current may result from abnormal operation of internal dynamic logic. Sampling Speed DFS0 DFS1 LRCK (fs) SCLK (Slave Mode) SCLK (Master Mode) MCLK Normal L L Double H L Quad L H 216kHz 64fs 64fs 64fs
54kHz 108kHz 128fs 64fs 128fs 64fs 256fs 128fs Table 1. System Clocks MCLK
LRCK (fs)
SCLK
32kHz 8.1920MHz 4.0960MHz 44.1kHz 11.2896MHz 5.6448MHz 48kHz 12.2880MHz 6.1440MHz 96kHz 12.2880MHz 6.1440MHz 192kHz 12.2880MHz 12.288MHz Table 2. Examples of System Clock Frequency
Serial Data Interface
The AK5394A supports four serial data formats that can be selected via SMODE1 and SMODE2 pins (Table 3). The data format is MSB-first, 2's complement. Figure Figure 1 Figure 2 Figure 3 Figure 4 SMODE2 L L H H SMODE1 Mode LRCK Lch = H, Rch = L Lch = H, Rch = L Lch = L, Rch = H Lch = L, Rch = H
L Slave Mode H Master Mode L I2S Slave Mode H I2S Master Mode Table 3. Serial I/F Formats
MS0137-E-03 - 13 -
2005/05
ASAHI KASEI
[AK5394A]
LRCK(i)
0 1 2 3 20 21 22 23 24 25 15 0 1 2 3 20 21 22 23 24 25 0 1
SCLK(i) FSYNC(i) SDATA(o)
23 22 21 4 3 2 1 0 23 22 21 7 43 2 1 0 23 22
Lch Data
Rch Data
FSYNC(i) SDATA(o)
23 22 5 4 3 2 1 0 23 22 5 4 3 2 1 0 23
23:MSB,0:LSB
Figure 1. Serial Data Timing (Slave Mode)
LRCK(o)
0 1 2 3 20 21 22 23 24 25 15 33 34 0 1 2 3 20 21 22 23 24 25 33 34 0 1
SCLK(o) FSYNC(o) SDATA(o)
23 22 5 4 3 2 1 0 23 22 5 4 3 2 1 0 23
Lch Data
Rch Data
23:MSB,0:LSB
Figure 2. Serial Data Timing (Master mode, Normal Speed Mode)
LRCK(i)
0 1 2 3 19 20 21 22 23 24 0 1 2 3 19 20 21 22 23 24 0 1
SCLK(i) SDATA(o)
23 22 6 5 4 3 2 1 0 23 22 6 5 4 3 2 1 0 23
Lch Data
Rch Data
23:MSB,0:LSB
Figure 3. Serial Data Timing (I2S Slave mode, FSYNC: Don't care)
LRCK(o)
0 1 2 3 20 21 22 23 24 25 15 33 34 0 1 2 3 20 21 22 23 24 25 33 34 0 1
SCLK(o) FSYNC(o) SDATA(o)
23 22 5 4 3 2 1 0 23 23 22 5 4 3 2 1 0 23
Lch Data
Rch Data
23:MSB,0:LSB
Figure 4. Serial Data Timing (I2S Master mode, Normal Speed Mode)
MS0137-E-03 - 14 -
2005/05
ASAHI KASEI
[AK5394A]
Offset Calibration
1. When the capacitors of 10F or less are connected between VREF pin and GND: When RSTN pin goes to "L", the digital section is powered-down. Upon returning "H", the offset calibration cycle is started. The offset calibration cycle should always be initiated after power-up. During the offset calibration cycle, the digital section of the part measures and stores the values of calibration input of each channel in registers. The calibration input value is subtracted from all future outputs. The calibration input may be obtained from either the analog input pins (AIN+/-) or the VCOM pins depending on the state of the ZCAL pin. With ZCAL "H", the analog input pin voltages are measured, and with ZCAL "L", the VCOM pin voltages are measured. The CAL output is "H" during calibration. 2. When capacitors more than 10F are connected between VREF pin and GND: The distortion at low frequency can be improved by connecting large capacitors (C in Figure 5) to VREF pins. (Refer to Figure 12) However, when the capacitors of VREF pins are larger than 10F, it is possibility that the offset calibration does not performed correctly if the offset calibration cycle is started right after power-up. Because the internal VREF can not settle to the appropriate voltage when the calibration cycle is completed. In this case, the offset calibration cycle should be started again after the VREF voltage settled. The timing is shown in Figure 6. Table 4 shows the relationship between the capacitance and the VREF settling time.
Capacitor C[F] 1000 470 220 100
Settling Time T[s]=5000 x C 5 2.4 1.1 0.5
Table 4. Settling Time and capacitors connected between VREF and GND
C C
+ +
1 0.22u 2
VREFL+ VREFL-
AK5394A
Figure 5. VREF circuit example
MS0137-E-03 - 15 -
2005/05
ASAHI KASEI
[AK5394A]
Settling Time of VREF pin:T(s) 0.005 x C
VA, VD
150ns~1ms tRTW RSTN
tRTV
tRCF
CAL tRCR
SDATA
Figure 6. Reset & Calibration Timing
Digital High Pass Filter
The AK5394A includes a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1Hz at fs=48kHz (Normal Speed Mode), at fs=96kHz (Double Speed Mode), at fs=192kHz (Quad Speed Mode) and also scales with sampling rate (fs) respectively. Sampling Speed Normal Double Quad DFS1 DFS0 fc (Cut-off frequency)
L L fs/48kHz L H fs/96kHz H L fs/192kHz Table 5. Cut-off frequency
MS0137-E-03 - 16 -
2005/05
ASAHI KASEI
[AK5394A]
SYSTEM DESIGN
Figure 7 and 8 show the system connection diagram. An evaluation board [AKD5394A] is available which demonstrates the optimum layout, power supply arrangements and measurement results.
C C + +C 0.22u VREFLVCOML AINL+ AINLZCAL VD DGND CAL RSTN SMODE2 SMODE1 LRCK SCLK VREFRVCOMR AINR+ 27 26 25 24 23 0.1u + 10u 7 0.1u 8 9 10 Mode Select fs System Controller 11 12 13 14 BGND DFS1 HPFE DFS0 MCLK FSYNC SDATA 21 20 19 18 17 16 15 AGND 22 0.22u Rch+ Rch+ 10u +5V Analog +C
1 0.22u + 2 0.22u 3 4 5 6
VREFL+
VREFR+
28
Lch+ Lch-
AK5394A
AINRVA
+3.3~5V Digital
Reset & Cal Control
System Ground
Analog Ground
Figure 7. Typical Connection Diagram Notes: - LRCK = fs, SCLK = 64fs. - Power lines of VA and VD should be distributed separately from the point with low impedance of regulator etc. - AGND, BGND and DGND must be connected to the same analog ground plane. - All digital input pins should not be left floating. - Refer Table 4 and Figure 12 about C.
Digital Ground Analog Ground
1 2 3 4 VREFL+ VREFLVCOML AINL+ AINLZCAL VD DGND CAL RSTN SMODE MCKS LRCK SCLK VREFR+ VREFRVCOMR AINR+ 28 27 26 25 24 23 22 21 20 19 18 17 16 15
System Controller
5 6 7 8 9 10 11 12 13 14
AK5394A
AINRVA AGND BGND DFS1 HPFE DFS0 MCLK FSYNC SDATA
Figure 8 Ground layout
MS0137-E-03 - 17 -
2005/05
ASAHI KASEI
[AK5394A]
1. Grounding and Power Supply Decoupling The AK5394A requires careful attention to power supply and grounding arrangements. Analog ground and digital ground of the system should be separate and connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5394A as possible, with the small value ceramic capacitor being the nearest. 2. On-chip Voltage Reference and VCOM The reference voltage for A/D converter is supplied from VREF+/- pin at AGND reference. A 0.22F ceramic capacitor should be attached between VREF+ and VREF-. An electrolytic capacitor (<1000F) should be connected between AGND and VREF+/- respectively to eliminate the effects of low frequency noise. Especially a ceramic capacitor should be as near to the pins as possible. And all digital signals, especially clocks, should be kept away from the VREF+/- pins in order to avoid unwanted coupling into the AK5394A. No load current may be taken from the VREF+/- pins. VCOM is a common voltage of the analog signal. In order to eliminate the effects of high frequency noise, a 0.22F ceramic capacitor should be connected as near to the VCOM pin as possible. And all signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK5394A. No load current may be drawn from the VCOM pin. 3. Analog Inputs Analog signal is differentially input into the modulator via the AIN+ and the AIN- pins. The input voltage is the difference between AIN+ and AIN- pins. The full-scale of each pin is nominally 2.4Vpp (typ). The AK5394A can accept input voltages from AGND to VA. The ADC output data format is 2's complement. The output code is 7FFFFFH (@24bit) for input above a positive full scale and 800000H (@24bit) for input below a negative full scale. The ideal code is 000000H (@24bit) with no input signal. The DC offset is removed by the offset calibration. The AK5394A samples the analog inputs at 128fs (6.144MHz@fs=48kHz, Normal Speed Mode). The digital filter rejects noise above the stop band except for multiples of 128fs. A simple RC filter may be used to attenuate any noise around 128fs and most audio signals do not have significant energy at 128fs. The AK5394A accepts +5V supply voltage. Any voltage which exceeds the upper limit of VA+0.3V and lower limit of AGND-0.3V and any current beyond 10mA for the analog input pins (AIN+/-) should be avoided. Excessive currents to the input pins may damage the device. Hence input pins must be protected from signals at or beyond these limits. Use caution specially in case of using 15V in other analog circuits.
MS0137-E-03 - 18 -
2005/05
ASAHI KASEI
[AK5394A]
4. External analog circuit Figure 9 shows an input buffer circuit example 1. (1st order HPF; fc=0.70Hz, 2nd order LPF; fc=320kHz, gain=-14.5dB). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC input, open JP1 and JP2 for XLR input). The input level of this circuit is +/-12.7Vpp (AK5394A: +/-2.4Vpp Typ.). When using this circuit, analog characteristics at fs=48kHz is DR=120dB, S/(N+D)=105dB.
4.7k 4.7k Analog In 12.7Vpp VP+
+
620 JP1 Vin68
1n 3.3k Bias
+
91
2.4Vpp AK5394 AIN+
VPNJM5534 XLR
NJM5534
2.2n 620
VA+ 10k Bias + 10k 10 0.1 VA=+5V VP=15V
JP2
68
1n 3.3k
+
91 AK5394 AIN-
Vin+
NJM5534 Bias
2.4Vpp
Figure 9. Analog input buffer circuit example 1
Fin 1Hz 10Hz Frequency Response -1.77dB -0.02dB Table 6. Frequency Response of HPF
Fin 20kHz 40kHz 80kHz 6.144MHz Frequency Response 0.00dB 0.00dB 0.00dB -51.36dB Table 7. Frequency Response of LPF
MS0137-E-03 - 19 -
2005/05
ASAHI KASEI
[AK5394A]
Figure 10 shows an input buffer circuit example 2. (1st order HPF; fc=0.66Hz, 1st order LPF; fc=590kHz, gain=-14dB). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC input, open JP1 and JP2 for XLR input). The input level of this circuit is +/-12.1Vpp (AK5394A: +/-2.4Vpp Typ.). When using this circuit, analog characteristics at fs=48kHz is DR=123dB, S/(N+D)=94dB.
12.1Vpp BNC JP1 Vin+ 22u 1k + NJM5534 VA XLR 4.7k 4.7k 10u JP2 Vin12.1Vpp 22u 1k 0.1u 4.7k Bias 4.7k 10k + NJM5534 AK5394 AIN180 2.4Vpp 1.0n 100 10k 2.4Vpp AK5394 AIN+
180
+ NJM5534
Figure 10. Analog input buffer circuit example 2
Fin 1Hz 10Hz Frequency Response -1.56dB -0.02dB Table 8. Frequency Response of HPF
Fin Frequency Response
20kHz 40kHz -0.005dB -0.02dB Table 9. Frequency
80kHz -0.08dB
6.144MHz -20.4dB
MS0137-E-03 - 20 -
2005/05
ASAHI KASEI
[AK5394A]
5. Measurement example Figure 11 plot is the THD+N vs Input Level with circuit Figure 9 and circuit Figure 10. X-AXIS is input level, Y-AXIS is THD+N (ratio). Measurement condition Ta=25C; VA=5.0V; VD=3.3V; AGND, BGND, DGND=0V; fs=48kHz; Input frequency=1kHz; 24 bit Output; Measurement frequency =10Hz 20kHz; DFS0="L", DFS1="L", VREF capacitors=1000F Measured by Audio Precision System Two.
A KM
-80 -82.5 -85 -87.5 -90 -92.5 -95 -97.5 d B -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -30
AK 5394A THD+N vs Input Level
Figure 10
Figure 9
-28
-26
-24
-22
-20
-18
-16 dB r
las t.at2c
-14
-12
-10
-8
-6
-4
-2
Figure 11. THD+N(ratio) vs. Input Level Figure 12 shows the relationship between THD+N and Frequency with capacitors on Table 4. Input circuit uses Figure 9. Measurement condition Ta=25C; VA=5.0V; VD=3.3V; AGND, BGND, DGND=0V; fs=48kHz; 24 bit Output; BW=10Hz 20kHz; DFS0="L", DFS1="L", Measured by Audio Precision System Two.
AK M
-60 -65 -70 -75 -80 -85 -90 d B F S -95 -100 -105 -110 -115 -120 -125 -130 10
A K5394A THD +N vs Frequency
220F
100F
10F
1000F
20
470F
50 100 200 500 Hz
la s t.at2 c
1k
2k
5k
10k
20k
Figure 12. THD+N vs. Frequency
MS0137-E-03 - 21 -
2005/05
ASAHI KASEI
[AK5394A]
6. Noise floor of AK5394A The AK5394A has a sprious noise of about -135dBFS on the noise floor of Lch output at no signal input. When this noise causes a trouble in system, it can be removed by adding a minute offset to the analog inputs of both channels externally using a circuit as Figure 13. The relationship between the frequency range (fT) of the sprious noise to be removed and the adding offset voltage (Vof) is fT [kHz] = 20 x Vof [mV] - 20. The example is shown in Table 10. Sprious noise Frequency Offset Voltage +2mV 0 20kHz +3mV 0 40kHz +5mV 0 80kHz Table 10. Sprious noise Frequency vs. Offset voltage A resistor, R in Figure 13 should be 8 to add an offset of 2mV to the analog inputs. The relationship between R and Vof is shown by the following equation.
Vof =
R x 5[V ] 20k + R
An offset voltage of the op-amps should be considered in the actual circuit. For example, when removing the sprious noise of 20kHz or less, the adding offset voltage should be 2+2=4mV if the op-amp has an offset of +/-2mV. In this case, the dynamic range of the ADC output decreases 4mV.
620 Vin5V 10k Bias+ R Bias+ 10k 10 0.1 Vin+
68 68
1n 3.3k Bias+
+
91 AK5394A AIN+
NJM5534
XLR
2.2n 620 1n 3.3k
+
91 AK5394A AIN-
NJM5534 Bias-
Figure 13. Removing the sprious noise circuit
MS0137-E-03 - 22 -
2005/05
ASAHI KASEI
[AK5394A]
PACKAGE
28pin SOP (Unit: mm)
10.4 0.3
7.5 0.2
1.095TYP 18.70.3 2.2 0.1
+0.1 0.15-0.05
0.10
0.40.1
0.12 M 0-10
Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate
MS0137-E-03 - 23 -
+0.1 0.1-0.05
1.27
0.75 0.2
2005/05
ASAHI KASEI
[AK5394A]
MARKING
AKM AK5394AVS
XXXBYYYYC
Contents of XXXBYYYYC XXXB: YYYYC: Lot # (X : numbers, B : alphabet ) Data Code (Y : numbers, C : alphabet)
Revision History
Date (YY/MM/DD) 02/01/09 02/07/22 05/03/08 Revision 00 01 02 Reason First Edition Add description Error Correct Page 22 7 19 22 05/05/10 03 Error Correct 24 Contents Add description of idol tone noise Condition of Analog Characteristics; External Circuit Figure 9 Figure 10 Polarity of analog signal in Figure 9. Vin+ Vin-, Vin- Vin+ Polarity of analog signal in Figure 13. Vin+ Vin-, Vin- Vin+ Date of Revision History: Revision 02: 04/03/08 05/03/08
MS0137-E-03 - 24 -
2005/05
ASAHI KASEI
[AK5394A]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0137-E-03 - 25 -
2005/05

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